Peripheral Frame 1 and Peripheral Frame 2 are grouped together to enable these blocks to be write/readperipheral block protected. The protected mode makes sure that all accesses to these blocks happen aswritten. Because of the pipeline, a write immediately followed by a read to different memory locations, willappear in reverse order on the memory bus of the CPU. This can cause problems in certain peripheralapplications where the user expected the write to occur first (as written). The CPU supports a blockprotection mode where a region of memory can be protected so that operations occur as written (thepenalty is extra cycles are added to align the operations). This mode is programmable and by default, itprotects the selected zones
DescriptionThe F2806x Piccolo™ family of microcontrollers provides the power of the C28x™ core and Control LawAccelerator (CLA) coupled with highly integrated control peripherals in low pin-count devices. This familyis code-compatible with previous C28x-based code, as well as providing a high level of analog integration.An internal voltage regulator allows for single-rail operation. Enhancements have been made to theHRPWM module to allow for dual-edge control (frequency modulation). Analog comparators with internal10-bit references have been added and can be routed directly to control the PWM outputs. The ADCconverts from 0 to 3.3-V fixed full scale range and supports ratio-metric VREFHI/VREFLO references. TheADC interface has been optimized for low overhead and latenc |
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