| A block diagram of the CC2533 is shown in Figure 8. The modules can be roughly divided into one of threecategories: CPU- and memory-related modules; modules related to peripherals, clocks, and power management;and radio-related modules. In the following subsections, a short description of each module that appears inFigure 8 is given.For more details about the modules and their usage, see the corresponding chapters in the CC253x User'sGuide (SWRU191).CPU and MemoryThe 8051 CPU core used in the CC253x device family is a single-cycle 8051-compatible core. It has threedifferent memory-access buses (SFR, DATA, and CODE/XDATA) with single-cycle access to SFR, DATA, andthe main SRAM. It also includes a debug interface and an 18-input extended interrupt unit.The interrupt controller services a total of 18 interrupt sources, divided into six interrupt groups, each of whichis associated with one of four interrupt priorities. Any interrupt service request is serviced also when the device isin idle mode b |
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