| Data word length: one to sixteen data bits•Four clocking schemes (controlled by clock polarity and clock phase bits) include:–Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of theSPICLK signal and receives data on the rising edge of the SPICLK signal.–Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.–Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of theSPICLK signal and receives data on the falling edge of the SPICLK signal.–Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of thefalling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.•Simultaneous receive and transmit operation (transmit function can be disabled in software)•Transmitter and receiver operations are accomplished through either interrupt-driven or polledalgorithms.•Nine SPI module control registers: Located in control register frame beginning at address 7040h.NOTEAll registers in this module are 16-bit registers that are connected to Peripheral Frame 2.When a register is accessed, the register data is in the lower byte (7–0), and the upper byte(15–8) is read as zeros. Writing to the upper byte has no effect.Enhanced feature:•4-level transmit/receive FIFO•Delayed transmit control•Bi-directional 3 wire SPI mode support•Audio data receive support via SPISTE inversio |
 |
|
手機(jī)站
您當(dāng)前位置是：產(chǎn)品大全 >> 電子元器件 >>
集成電路(IC)
免責(zé)聲明：以上所展示的信息由會員自行提供，內(nèi)容的真實(shí)性、準(zhǔn)確性和合法性由發(fā)布會員負(fù)責(zé)，www.qy6.com對此不承擔(dān)任何責(zé)任。如有侵犯您的權(quán)益，請來信通知刪除。
聯(lián)系信息
