Loss of Input Clock (NMI Watchdog Function)The2806xdevicesmaybeclockedfromeitheroneoftheinternalzero-pinoscillators(INTOSC1/INTOSC2), the on-chip crystal oscillator, or from an external clock input. Regardless of theclock source, in PLL-enabled and PLL-bypass mode, if the input clock to the PLL vanishes, the PLL willissue a limp-mode clock at its output. This limp-mode clock continues to clock the CPU and peripherals ata typical frequency of 1–5 MHz.When the limp mode is activated, a CLOCKFAIL signal is generated that is latched as an NMI interrupt.Depending on how the NMIRESETSEL bit has been configured, a reset to the device can be firedimmediately or the NMI watchdog counter can issue a reset when it overflows. In addition to this, theMissing Clock Status (MCLKSTS) bit is set. The NMI interrupt could be used by the application to detectthe input clock failure and initiate necessary corrective action such as switching over to an alternativeclock source (if available) or initiate a shut-down procedure for the system.If the software does not respond to the clock-fail condition, the NMI watchdog triggers a reset after apreprogrammed time interval. Figure 2-15 shows the interrupt mechanisms involved.
CPU-Watchdog ModuleThe CPU-watchdog module on the 2806x device is similar to the one used on the 281x/280x/283xxdevices. This module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bitwatchdog up counter has reached its maximum value. To prevent this, the user must disable the counteror the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register that resetsthe watchdog counter. Figure 2-16 shows the various functional blocks within the watchdog modul |
 |
|
手機站
您當前位置是：產品大全 >> 電子元器件 >>
集成電路(IC)
免責聲明：以上所展示的信息由會員自行提供，內容的真實性、準確性和合法性由發布會員負責，www.qy6.com對此不承擔任何責任。如有侵犯您的權益，請來信通知刪除。
聯系信息
